| 书目名称 | Wafer-Level Chip-Scale Packaging | | 副标题 | Analog and Power Sem | | 编辑 | Shichun Qu,Yong Liu | | 视频video | | | 概述 | Covers the development of wafer level power discrete packaging with regular wafer level design concept and directly bumping technology.Introduces the development of the analog and power SIP/3D/TSV/sta | | 图书封面 |  | | 描述 | Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the roleof modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the b | | 出版日期 | Book 2015 | | 关键词 | Analog Technology; Analog and Power Electronic Package; Packaging Technology; Power Electronics; WLCSP A | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4939-1556-9 | | isbn_softcover | 978-1-4939-5438-4 | | isbn_ebook | 978-1-4939-1556-9 | | copyright | Springer Science+Business Media New York 2015 |
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发表于 2025-3-21 17:56:06
