Titlebook: Hot-Carrier Reliability of MOS VLSI Circuits; Yusuf Leblebici,Sung-Mo (Steve) Kang Book 1993 Springer Science+Business Media New York 1993

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Transistor-Level Simulation for Circuit Reliability,der to account for the influence of hot-carrier effects upon circuit-level reliability, the next step will be to extend the analytical reliability estimation models developed in the previous chapters to circuit-level applications.

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Circuit Design for Reliability,out to improve the resistance of the devices to degradation. A number of simulation approaches for estimating hot-carrier reliability, ranging from two-dimensional device simulation, to circuit simulation, and to large-scale timing simulation, were examined in detail in Chapters 4 through 6.

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Book 1993becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada­ tion of MOS transistor char

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Fast Timing Simulation for Circuit Reliability,conventional circuit simulation, have been examined in Chapter 5. However, the detailed circuit simulation needed for determining the stress conditions of individual devices restricts the computational efficiency of reliability simulation approaches for very large-scale integrated circuits.

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Modeling of Damaged Mosfets,gradation of circuit performance over time. The extent of the hot-carrier damage each transistor experiences is determined by its terminal voltage waveforms, i.e., by the operating conditions of the circuit. Consequently, the mechanism of hot-carrier induced device degradation must be examined within the context of circuit simulation.