Titlebook: Delay Fault Testing for VLSI Circuits; Angela Krstić,Kwang-Ting Cheng Book 1998 Springer Science+Business Media New York 1998 VLSI.compute

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Test Application Schemes for Testing Delay Defects,tors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.

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Design for Delay Fault Testability,umber of faults that can be guaranteed to be detected independent of delays outside the target path, etc. This chapter describes design for testability techniques such as test point insertion and use of partial scan as well as techniques for resynthesizing the circuit such that its path delay fault testability is improved.

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Rhinomanometrische Untersuchungene used for representing delay defects lumped at gates while the path and segment delay models address defects that are distributed over several gates. The advantages and disadvantages of each model are discussed.