Titlebook: Delay Fault Testing for VLSI Circuits; Angela Krstić,Kwang-Ting Cheng Book 1998 Springer Science+Business Media New York 1998 VLSI.compute

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Delay Fault Testing for VLSI Circuits978-1-4615-5597-1Series ISSN 0929-1296

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https://doi.org/10.1007/978-1-4615-5597-1VLSI; computer-aided design (CAD); design; integrated circuit; modeling; quality; simulation; stability

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0929-1296 gnal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay te

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Die Bedeutung der gestörten Nasenatmungtors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.