Titlebook: Delay Fault Testing for VLSI Circuits; Angela Krstić,Kwang-Ting Cheng Book 1998 Springer Science+Business Media New York 1998 VLSI.compute

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Introduction, testing has evolved from the common problem faced by the semiconductor industry: designs that function properly at low clock frequencies fail at the rated speed. As experiments show, tests that do not specifically target delay faults have a limited success in detecting timing defects [21, 107, 108,

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Test Application Schemes for Testing Delay Defects,ed it is necessary to know how these tests will be applied to the circuit. The testing strategy depends on the type of the circuit (combinational, scan, non-scan or partial scan sequential) as well as on the speed of the testing equipment. Ordinarily, testing delay defects requires that the test vec

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Delay Fault Simulation,generated fault simulation should be performed to cover as many faults as possible with the same test. Delay fault simulation can also be performed with functional, random, stuck-at or any other available set of vectors to determine the delay fault coverage and reduce the delay test generation effor

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Test Generation for Path Delay Faults,robust, validatable non-robust and functional sensitizable faults are considered as single path delay faults. These paths usually can be tested with many different tests, i.e., there are many different robust tests for a robust testable path, many different non-robust tests for a non-robust testable

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Design for Delay Fault Testability,ably low, most of the research in this area has concentrated on improving the path delay fault testability. Path delay fault testability can be defined with respect to several factors: the number of faults to be tested, the number of tests that need to be applied to test all path delay faults, the n

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Conclusions and Future Work,in designs in which performance specifications can be violated by very small defects. Studies show that high stuck-at fault coverage is not sufficient to guarantee detection of these timing failures. The use of traditional fault models and testing strategies becomes even more inadequate as the curre

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https://doi.org/10.1007/978-3-658-09738-7 testing has evolved from the common problem faced by the semiconductor industry: designs that function properly at low clock frequencies fail at the rated speed. As experiments show, tests that do not specifically target delay faults have a limited success in detecting timing defects [21, 107, 108,