Titlebook: Correct Hardware Design and Verification Methods; 10th IFIP WG10.5 Adv Laurence Pierre,Thomas Kropf Conference proceedings 1999 Springer-Ve

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Formal Verification of Explicitly Parallel Microprocessorsel. We then describe how to formally verify that the model implements the instruction set. The contribution of this paper is a specification and verification method that facilitates the decomposition of microarchitectural correctness proofs using instruction-set extensions.

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Efficient Decompositional Model Checking for Regular Timing Diagramsar in the system size and a small polynomial in the representation of the diagram. The algorithm can be easily used with symbolic (BDDbased) model checkers. We illustrate the workings of our algorithm with the verification of a simple master-slave system.

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