Titlebook: Correct Hardware Design and Verification Methods; 10th IFIP WG10.5 Adv Laurence Pierre,Thomas Kropf Conference proceedings 1999 Springer-Ve

obscurity

Esterel and Jazz : Two Synchronous Languages for Circuit Designgrams are imperative, concurrent, and preemption based. Programs are translated into circuits that are optimized using specific sequential optimization algorithms. A verification system restricted to the pure control part of programs is available. Esterel is currently used by several CAD vendors and

hypotension

Design Process of Embedded Automotive Systems—Using Model Checking for Correct Specificationsn processes can not cope with this complexity. In the first part of this paper we show the current development-process at BMW, the second part deals with our results of using model checking to verify .-models.

吝啬性

积习已深

Formal Verification of Explicitly Parallel Microprocessorsmemory access,or multimedia instructions—that allow the compiler or programmer to express more instruction-level parallelism than the microarchitecture is willing to derive. In this paper we show how these instruction-set extensions can be put to use when formally verifying the correctness of a micr

Forage饲料

Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpsuper- scalar processors. We achieve a significant speedup in the verification of such processors, compared to the result by Burch [.], while using an entirely automatic tool. Instrumental to our success are exploiting the properties of positive equality [.][.] and the simplification capabilities of

arousal

吞没

Efficient Decompositional Model Checking for Regular Timing Diagramsnotation is often more convenient than the use of temporal logic or automata. We introduce a class of timing diagrams called .. RTD’s have a precise syntax, and a formal semantics that is simple and corresponds to common usage. Moreover, RTD’s have an inherent compositional structure, which is explo

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Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaar [.] that the method has potential to increase the capacity of formal verification tools for hardware.In this paper,we examine this potential in light of an experiment in the opposite direction: the application of symbolic model checking to railway interlocking software previously verified with Stål

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