Titlebook: Computer Engineering and Technology; 20th CCF Conference, Weixia Xu,Liquan Xiao,Zhenzhen Zhu Conference proceedings 2016 Springer Nature Si

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书目名称Computer Engineering and Technology影响因子(影响力)




书目名称Computer Engineering and Technology影响因子(影响力)学科排名




书目名称Computer Engineering and Technology网络公开度




书目名称Computer Engineering and Technology网络公开度学科排名




书目名称Computer Engineering and Technology被引频次




书目名称Computer Engineering and Technology被引频次学科排名




书目名称Computer Engineering and Technology年度引用




书目名称Computer Engineering and Technology年度引用学科排名




书目名称Computer Engineering and Technology读者反馈




书目名称Computer Engineering and Technology读者反馈学科排名

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W. Erwin Diewert,Denis A. Lawrence-bit coarse directory, 22% overhead of share list can be avoided at the expense of 0.16% average performance loss on average; compared to 8-bit coarse directory, 48% invalid messages are saved and the performance is improved by 2.31%.

初次登台

https://doi.org/10.1057/9780230375260he efficiency of our implementation of NKICA on the MIC architecture, and show that it achieves a consistent speedup rate of around 10 on average, and of 12.3 at best, comparing with that performed on single CPU.

极小量

SHOCK

BFDir: A Space-Efficient Coherence Directory Based on Bloom Filter-bit coarse directory, 22% overhead of share list can be avoided at the expense of 0.16% average performance loss on average; compared to 8-bit coarse directory, 48% invalid messages are saved and the performance is improved by 2.31%.

Carcinoma

Carcinoma

Single/Double Precision Floating-Point Division and Square Root Unit Based on SRT-8 Algorithm-precision/SIMD single-precision floating-point division and square root operation based on SRT-8 algorithm was introduced. Special instructions were designed and independent mantissa computing unit and normalization unit are implemented. Moreover, parallel adders and QDS structure was adopted to hi

轮流

FLAGR

A Methodology for Performance Verification of Microprocessorsten introduced during the design stages. In order to identify and fix the performance defects, a hierarchical performance verification methodology is proposed. Parameter sensitive performance models and coverage driven stimulus are built at the unit-level. Implementation oriented performance calibra

下船

A Novel L1 Cache Based on Volatile STT-RAMscalability, high density and low leakage power. Nevertheless, the current non-volatile STT-RAM cache architecture also has some drawbacks, such as long write latency and high write energy, which limit the application of STT-RAM in the top level cache design. To solve these problems, we relax the re