Titlebook: VHDL Modeling for Digital Design Synthesis; Yu-Chin Hsu,Kevin F. Tsai,Eric S. Lin Book 1995 Springer Science+Business Media New York 1995

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Modeling at the RT Level,ship between the RTL constructs in VHDL and the logic which is synthesized. It focuses on code styles that will give the best performance for an RTL synthesis tool. An RTL synthesis tool produces registered and combinational logic at the RTL level.

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Modeling at the FSMD Level,troller provides the datapath with the appropriate commands at every moment in time so that the datapath properly implements the specified functions and produces the required external output signals. The controller uses status conditions from the datapath to serve as decision variables for determining the sequence of state transitions.

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Introduction,evels of abstraction. Traditional paper-and-pencil and capture-and-simulate methods have largely given way to the describe-and-synthesize approach for these reasons. In this chapter, we will first briefly overview the digital design process. Then, we will discuss the levels of abstraction of a desig

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