Titlebook: SystemVerilog Assertions and Functional Coverage; Guide to Language, M Ashok B. Mehta Book 20141st edition Springer Science+Business Media

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Ashok B. Mehtare frequently. This is, among other things, reflected in the names of the two former conference series (the so- ware product line conference series, started in 2000 in the USA, and the product family engineerin978-3-642-06364-0978-3-540-28901-2

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Introduction,f high performance and low power and small area result in ever so complex design architecture. Multi-core, multi-threading and Power, Performance and Area (PPA) demands exacerbate the design complexity and functional verification thereof.

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Functional Coverage,covered everything that needs to be covered? That’s where Functional Coverage comes into picture. But first let us make sure we understand the difference between the good old Code Coverage and the new Functional Coverage methodology.

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Immediate Assertions,Immediate assertions are simple non-temporal domain assertions that are executed like statements in a procedural block. Interpret them as an expression in the condition of a procedural ‘if’ statement. Immediate assertions can be specified only where a procedural statement is specified.

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Sampled Value Functions $rose, $fell,These sampled value functions allow for antecedent and/or the consequent to be edge triggered. $rose means that the expression (in $rose(expression)) was sampled to be ‘0’ (or ‘x’ or ‘z’) at the previous clk edge (previous meaning the immediately preceding clk from current clk) and that it is sampled ‘1’ at this clk edge.