| 书目名称 | SystemVerilog Assertions and Functional Coverage | | 副标题 | Guide to Language, M | | 编辑 | Ashok B. Mehta | | 视频video | | | 概述 | Covers both SystemVerilog Assertions and Sytem Verilog Functional Coverage language and methodologies.Provides practical examples of the what, how and why of Assertion Based Verification and Functiona | | 图书封面 |  | | 描述 | This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug. | | 出版日期 | Book 20141st edition | | 关键词 | Assertion Based Verifiction; Design Debug; Functional Hardware verification; IEEE 1800 SystemVerilog; Sy | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4614-7324-4 | | isbn_ebook | 978-1-4614-7324-4 | | copyright | Springer Science+Business Media New York 2014 |
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发表于 2025-3-21 16:47:54
