书目名称 | Low-Power High-Speed ADCs for Nanometer CMOS Integration |
编辑 | Zhiheng Cao,Shouli Yan |
视频video | |
概述 | Implementation detail of three state-of-the-art low-power high-performance ADC and clock multiplier PLL designs using unique architectures.Concise and graphical explanation of key points in ADC/PLL de |
丛书名称 | Analog Circuits and Signal Processing |
图书封面 |  |
描述 | .Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. .1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm.2.. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input...2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. ..3) A 0.4ps-rms-jitter (integrated from 3kHz to 30 |
出版日期 | Book 2008 |
关键词 | Analog-to-digital converters; CMOS; Clock-multipliers; Deep-submicron CMOS; Filter; Multiplexer; Nanometer |
版次 | 1 |
doi | https://doi.org/10.1007/978-1-4020-8450-8 |
isbn_softcover | 978-90-481-7885-8 |
isbn_ebook | 978-1-4020-8450-8Series ISSN 1872-082X Series E-ISSN 2197-1854 |
issn_series | 1872-082X |
copyright | Springer Science+Business Media B.V. 2008 |