| 书目名称 | Low-Power Deep Sub-Micron CMOS Logic |
| 副标题 | Sub-threshold Curren |
| 编辑 | P. R. Meer,A. Staveren,A. H. M. Roermund |
| 视频video | |
| 概述 | Classifies all power dissipation sources in digital CMOS circuits.Provides for a systematic approach of power reduction techniques.A clear distinction between power dissipated to perform a calculation |
| 丛书名称 | The Springer International Series in Engineering and Computer Science |
| 图书封面 |  |
| 描述 | 1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore‘s Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is |
| 出版日期 | Book 2004 |
| 关键词 | CMOS; SECS 841; Transistor; integrated circuit; logic; van der Meer; zitter |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4020-2849-6 |
| isbn_softcover | 978-1-4757-1057-1 |
| isbn_ebook | 978-1-4020-2849-6Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Springer Science+Business Media New York 2004 |
发表于 2025-3-21 17:17:43
