| 书目名称 | Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip | | 编辑 | Pascal Meinerzhagen,Adam Teman,Alexander Fish | | 视频video | | | 概述 | Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applications;.Models the statistical retention time distribution of GC-eDRAM and validates the model by silicon | | 图书封面 |  | | 描述 | .This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.. | | 出版日期 | Book 2018 | | 关键词 | Memory Systems; Memory for VLSI; embedded DRAM memory; embedded memory design; memory optimization; error | | 版次 | 1 | | doi | https://doi.org/10.1007/978-3-319-60402-2 | | isbn_softcover | 978-3-319-86855-4 | | isbn_ebook | 978-3-319-60402-2 | | copyright | Springer International Publishing AG 2018 |
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发表于 2025-3-21 16:10:12
