Titlebook: Cryptographic Hardware and Embedded Systems -- CHES 2013; 15th International W Guido Bertoni,Jean-Sébastien Coron Conference proceedings 20

compel

Inkling

Matthew Winslade,Graham Daniel,Jacqui Hoodin 72,300 and 47,900 clock cycles, respectively; and a protected single-core scalar multiplication in 114,800 cycles. These numbers improve by around 2% on the newer Core i7 2.8GHz Ivy Bridge platform.

压倒性胜利

An Accurate Probabilistic Reliability Model for Silicon PUFsted distributions describe the empirically observed data statistics almost perfectly, even considering sensitivity to operational temperature. This allows studying PUF reliability behavior in full detail, including average and . probabilities, and is an invaluable tool for designing more efficient and better adapted PUFs and PUF-based systems.

TEN

On the Effectiveness of the Remanence Decay Side-Channel to Clone Memory-Based PUFsof independent interest, we show how to use our evaluation results to significantly improve the performance of the recently proposed TARDIS scheme, which is based on remanence decay in SRAM and used as a time-keeping mechanism for low-power clock-less devices.

基因组

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFIDas a power consumption of 12.5 .W at 1 MHz on a low leakage 130 nm CMOS process technology. As a result, we provide a design that needs 40% less resources than related work. Our design is even smaller than the smallest SHA-1 and SHA-2 implementations.