Titlebook: Cryptographic Hardware and Embedded Systems -- CHES 2013; 15th International W Guido Bertoni,Jean-Sébastien Coron Conference proceedings 20

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On Measurable Side-Channel Leaks Inside ASIC Design Primitivesetric layout of the memory matrix structure is measurable. It is a leak correlated to integer representation of the memory address. We also show that a ROM-based countermeasure (Dual-rail RSL memory [10]) becomes vulnerable with the geometric leak. A general transistor-level design method to counter

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Smaller Keys for Code-Based Cryptography: QC-MDPC McEliece Implementations on Embedded Devices and decryption on the FPGA, we achieved a very compact implementation on the microcontroller using only 4,800 and 9,600 bits for the public and secret key at 80 bits of equivalent symmetric security.

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Cryptographic Hardware and Embedded Systems -- CHES 201315th International W

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Conference proceedings 2013ara, CA, USA, in August 2013. The 27 papers presented were carefully reviewed and selected from 132 submissions. The papers are organized in the following topical sections: side-channel attacks; physical unclonable function; lightweight cryptography; hardware implementations and fault attacks; effic

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Kim Wilson,Nerida Wayland,Amy Murphyut. The number of elementary modular operations is significantly reduced: a factor 12 to 26 for multiplications and 6 to 21 for additions. Virtex 5 FPGAs implementations show that for a similar area, our plus-minus RNS modular inversion is 6 to 10 times faster.