Titlebook: Computer-Aided Verification; 2nd Internatonal Con Edmund M. Clarke,Robert P. Kurshan Conference proceedings 1991 Springer-Verlag Berlin Hei

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Vectorized model checking for computation tree logic,essors. Although efficient recursive model checking algorithms for CTL, which run in time proportional to both the size of Kripke structures and the length of formulas, have been already proposed [7, 2], their algorithms cannot be vectorized due to recursive procedure calls. In this paper we propose

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Introduction to a computational theory and implementation of sequential hardware equivalence,tate equivalence (∼), alignability, resetability, and sequential hardware equivalence (≈). This theory is motivated by (1) the observation that it is impossible to control the initial state of a machine when it is powered on, and (2) the desire to decide equivalence of two designs based solely on th

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Manifest

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Automated RTL verification based on predicate calculus,vior, specification, and hypotheses on its clock sequencing are modelled using a special kind of predicate calculus formulas, named transfer formulas. The proof process consists in applying two general rules of the predicate calculus in a specific order. The automated verification process uses an ac

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哄骗

Quantitative temporal reasoning,uires the expression of time-critical properties that relate the occurrence of events of the system. We focus on the formal specification and reasoning about the correctness of such programs. We popose a system of temporal logic, RTCTL (Real-Time Computation Tree Logic), that allows the melding of q

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Using partial-order semantics to avoid the state explosion problem in asynchronous systems,onsequential processes with well-behaved nondeterministic choice. A specification strategy based on partial orders allows precise description of the . and . structure of processes. Process behaviors are modelled by pomsets, but (discrete) sets of pomsets with implicit branching structure are replace

Postulate

A stubborn attack on state explosion,al logic specifications. The method facilitates the generation of . such that the truth values of a collection of linear temporal logic formulas are the same in the ordinary and reduced state spaces. The only restrictions posed by the method are that the collection of formulas must be known before t