Titlebook: Computer Aided Verification; 33rd International C Alexandra Silva,K. Rustan M. Leino Conference proceedings‘‘‘‘‘‘‘‘ 2021 The Editor(s) (if

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Automated Safety Verification of Programs Invoking Neural Networkscomponents implemented using diverse technologies. This shortcoming is pinpointed by programs invoking neural networks despite their acclaimed role as innovation drivers across many application areas. In this paper, we embark on the verification of system-level properties for systems characterized b

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Verisig 2.0: Verification of Neural Network Controllers Using Taylor Model Preconditioningctivations and develop a Taylor-model-based reachability algorithm through Taylor model preconditioning and shrink wrapping. Furthermore, we provide a parallelized implementation that allows Verisig 2.0 to efficiently handle larger NNs than existing tools can. We provide an extensive evaluation over

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Grating

PEREGRiNN: Penalized-Relaxation Greedy Neural Network Verifierted as well as adversarial misclassifications can result in fatal outcomes. As a consequence, techniques of formal verification have been recognized as crucial to the design and deployment of safe NNs. In this paper, we introduce a new approach to formally verify the most commonly considered safety

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Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models verification. They should define the allowed sequential and relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration of full-scale instruction-set architecture (ISA) semantics with axiomatic concurrency models, either in mathematics or in tools. These ISA semanti

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Summing up Smart Transitionsgrity of currencies and transactions. For example, the sum of balances should not be changed by a transfer operation. Currencies manipulated by code present a verification challenge to mathematically prove their integrity by reasoning about computer programs that operate over them, e.g., in Solidity

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Stateless Model Checking Under a Reads-Value-From Equivalenceonentially large spaces of thread interleavings, SMC attempts to partition this space into equivalence classes and explore only a few representatives from each class. The efficiency of this approach depends on two factors: (a) the coarseness of the partitioning, and (b) the time to generate represen