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Titlebook: Closing the Power Gap between ASIC & Custom; Tools and Techniques David Chinnery,Kurt Keutzer Book 2007 Springer-Verlag US 2007 ASIC.algori

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https://doi.org/10.1007/978-1-4899-0327-3ASIC design methodologies are fast catching up with custom design methodologies..An economic driver for ASICs is the increasing demand for mobile and consumer devices. These devices have smaller form factors. They are becoming part of everyday life with high usage, and need to be robust. For example
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https://doi.org/10.1007/978-0-387-68953-1ASIC; algorithms; automation; consumption; design automation; integrated circuit; optimization; programming
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978-1-4419-3833-6Springer-Verlag US 2007
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Overview of the Factors Affecting the Power Consumption,to 0.13um CMOS. A variety of factors cause synthesizable designs to consume 3 to 7× more power. We discuss the shortcomings of typical synthesis flows, and changes to tools and standard cell libraries needed to reduce power. Using these methods, we believe that the power gap between ASICs and custom
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Pipelining to Reduce the Power,thmic and architectural choices to find a low power implementation that meets performance requirements for the target application..Circuit designers explore trade-offs for different microarchitectural features that implement a given architecture for typical applications. The analysis may be detailed
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