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Titlebook: 3D Interconnect Architectures for Heterogeneous Technologies; Modeling and Optimiz Lennart Bamberg,Jan Moritz Joseph,Thilo Pionteck Book 20

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https://doi.org/10.1007/978-3-658-09575-8circuits (ICs) have been introduced. This part introduces orthogonal optimizations on the system level, focusing on networks on chips (NoCs) for communication. As the optimizations are complementary, both can be combined to multiply the given gains, which we will do in our concluding Chap. ..
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https://doi.org/10.1007/978-3-658-09679-3s). We observed that routers in digital layers could be clocked faster. Thus, we proposed a heterogeneous routing to improve latency by increasing the number of hops in layers fabricated in advanced technology nodes, for a hop reduction in layers fabricated in less-scaled technology nodes (e.g., mix
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