Titlebook: VLSI for Embedded Intelligence; Proceedings of the 2 Anu Gupta,Jai Gopal Pandey,Devesh Dwivedi Conference proceedings 2025 The Editor(s) (i

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Optimized Composite Field-Based Hardware Architectures for AES S-Box Using Logic Decomposition Techare logic synthesis approaches useful in reducing the support size of complex Boolean functions with more literals. The functional decomposition techniques in this work are applied to the multiplicative inverse function of the AES S-box constructed using sub-field arithmetic based on a normal basis.

penance

蛤肉

合同

,B-Box: An Efficient and Configurable RISC-V Bit Manipulation IP Generator,ectures (DSA) in mainstream computing. The recent advent of an open and flexible ISA like RISC-V has further endorsed this change and provided the means to make DSA a reality. With Security and Safety being the forerunners in today’s DSA trends, one would find that most applications catering to thes

heartburn

过度

,FPGA Implementation of Resource-Efficient Cube Calculation Architecture Using Yavadunam Sutra, operations. Among these operations, the multiplier plays a pivotal role, particularly in evaluating cube operands. This paper introduces a new low-resource cube calculation architecture that utilizes a proposed cube calculation algorithm based on the Yavadunam sutra. The suggested algorithm elimina

transdermal

A Hybrid BAT Algorithm for Scheduling Droplet Mixing Operations in Digital Microfluidic Biochips,acy and time in a very small space. DMFBs provide a variety of advantages over traditional laboratory techniques, including cost reductions, enhanced automation, software programmability, and almost 100% precision. The scheduling of microfluidic activities, like floor-planning and pin assignment, mo

责难

,LightLock: Ensuring Hardware IP Security in IoT Environment with Lightweight Logic Locking,al properties (IPs) can severely jeopardize the integrity of the semiconductor supply chain. In response to these challenges, logic locking has emerged as a critical design for trust (DfTr) strategy, ensuring that ICs attain full functionality exclusively through unlocking with an on-chip secret key

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Indigenous Development of SPARC Processor-Based Radar Controller (SPRC) ASIC, been developed for ISRO’s various Microwave Synthetic Aperture Radar (SAR) missions. SPRC ASIC is used in RADAR Controller (RC) subsystem design which command and control the Radar operation. The SPRC ASIC is based on 32-bit SPARC V8 compliant processor with a 32-bit IEEE-754 compliant Floating-Poi

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