Titlebook: Understanding Behavioral Synthesis; A Practical Guide to John P. Elliott Book 1999 Springer Science+Business Media New York 1999 ASIC.FPGA.

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Reusable Test Benches,Behavioral synthesis allows designers to evaluate alternative hardware architectures with differing clock periods, resources and I/O timing. Based on these user-specified constraints, behavioral synthesis tools schedule operations and produce designs that meet those constraints.

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Case Study: JPEG Compression,This chapter discusses an example design that implements a JPEG compression algorithm.JPEG is a compression standard developed for grayscale and color continuous-tone still images.

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Case Study: FIR Filter,This chapter discusses an example design that implements a Finite Impulse Response (FIR) digital filter. Digital filtering is an important aspect of most DSP-oriented designs. This filter can be easily described using a behavioral coding style and the results of behavioral synthesis are easily understood.

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Case Study: Viterbi Decoding,This chapter discusses the implementation of a Viterbi decoding algorithm. The Viterbi decoding algorithm is used to decode convolution codes and is found in many systems that receive digital data that might contain errors.

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