| 书目名称 | The Complete Verilog Book |
| 编辑 | Vivek Sagdeo |
| 视频video | http://file.papertrans.cn/907/906507/906507.mp4 |
| 图书封面 |  |
| 描述 | The Verilog hardware description language (HDL) provides the ability to describe digital and analog systems. This ability spans the range from descriptions that express conceptual and architectural design to detailed descriptions of implementations in gates and transistors. Verilog was developed originally at Gateway Design Automation Corporation during the mid-eighties. Tools to verify designs expressed in Verilog were implemented at the same time and marketed. Now Verilog is an open standard of IEEE with the number 1364. Verilog HDL is now used universally for digital designs in ASIC, FPGA, microprocessor, DSP and many other kinds of design-centers and is supported by most of the EDA companies. The research and education that is conducted in many universities is also using Verilog. This book introduces the Verilog hardware description language and describes it in a comprehensive manner. Verilog HDL was originally developed and specified with the intent of use with a simulator. Semantics of the language had not been fully described until now. In this book, each feature of the language is described using semantic introduction, syntax and examples. Chapter 4 leads to the full semant |
| 出版日期 | Book 1998 |
| 关键词 | Hardware; Hardwarebeschreibungssprache; RTL; Standard; Verilog; algorithms; analog; data types; formal metho |
| 版次 | 1 |
| doi | https://doi.org/10.1007/b116655 |
| isbn_softcover | 978-1-4757-7126-8 |
| isbn_ebook | 978-0-306-47658-7 |
| copyright | Springer Science+Business Media New York 1998 |
|Archiver|手机版|小黑屋|
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