| 书目名称 | SVA: The Power of Assertions in SystemVerilog | | 编辑 | Eduard Cerny,Surrendra Dudani,Dmitry Korchemny | | 视频video | | | 概述 | Provides a comprehensive guide to assertion-based verification with System Verilog Assertions (SVA).Includes step-by-step examples of how SVA can be used to construct powerful and reusable sets of pro | | 图书封面 |  | | 描述 | .This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012..System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and | | 出版日期 | Book 2015Latest edition | | 关键词 | Assertion Based Verifiction; Design Debug; Functional Hardware Verification; IEEE 1800-2012 SystemVeril | | 版次 | 2 | | doi | https://doi.org/10.1007/978-3-319-07139-8 | | isbn_softcover | 978-3-319-33109-6 | | isbn_ebook | 978-3-319-07139-8 | | copyright | Springer International Publishing Switzerland 2015 |
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发表于 2025-3-21 16:24:56
