Titlebook: Reconfigurable Computing: Architectures, Tools, and Applications; 4th International Wo Roger Woods,Katherine Compton,Pedro C. Diniz Confere

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Optimal Unroll Factor for Reconfigurable Architecturesfigurable fabric. We assume the Molen machine organization and Molen programming paradigm as our framework. The proposed algorithm computes the optimal unroll factor . for a loop that contains a hardware kernel . such that . instances of . run in parallel on the reconfigurable hardware, and the targ

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Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systemsarchitecture implements a flexible memory subsystem based on software controlled scratchpad shared memory banks. The main concern of the paper is shared memory management as it is a dominant factor in current designs and influences the performance of embedded systems as well as their energy consumpt

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Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension up a large table and processing one match per query. In this paper, we propose a systolic array approach to detect string matches without using looking up tables. The pipelining systolic array is implemented as a multi-seeds detection and parallel extension pipeline engine to accelerate the first t

MAG

Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAsown malicious pattern database. Traditional static pattern descriptions may not efficiently represent sophisticated attack signatures. Recently, most NIDSs have adopted regular expressions such as Perl compatible regular expressions (PCREs) to describe an attack signature, especially for polymorphic

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A Custom Processor for a TDMA Solver in a CFD Application TDMA (Tri-Diagonal Matrix Algorithm) for solving a tri-diagonal system of equations. The custom processor was implemented in a commercial PCI prototyping board based on Virtex4LX FPGAs and uses a dedicated memory cache system, address generators and a deep pipelined floating-point datapath. Running

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A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementationt scientific computing applications. One type of calculation that is commonplace in scientific computation is the solution of systems of linear equations. A method that has proven in software to be very efficient and robust for finding such solutions is the Conjugate Gradient algorithm. In this pape

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Physical Design of FPGA Interconnect to Prevent Information Leakageque to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These nov

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Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs across multiple processors controlled by a single hardware scheduler. This approach increases the performance of software at a minimal cost to hardware. The issues that must be addressed for extending a uniprocessor kernel include system initialization, processor identification, context switching a