Titlebook: On-Chip Inductance in High Speed Integrated Circuits; Yehea I. Ismail,Eby G. Friedman Book 2001 Kluwer Academic Publishers 2001 CMOS.Count

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Equivalent Elemore Delay for , Trees,s shown in Figure 7.1. Thus, the process of characterizing signal waveforms in tree and zigzag structured interconnect is of primary importance. One of the more popular delay models used within industry for analyzing the temporal properties of . trees is the Elmore delay model [74], [75]. Despite no

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Exploiting On-Chip Inductance in High Speed Clock Distribution Networks,e introduction of new materials for low resistance interconnect [46]-[62]. These increasing inductance effects are typically viewed as an additional problem which must be managed. This perspective is accurate in many respects. Dealing with inductance requires efficient inductance extraction methods

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Accurate and Efficient Evaluation of the Transient Response in , Circuits: The DTT Method,ions for . trees are discussed in 3.1. An equivalent Elmore delay model for . trees is presented in Chapter 7. These models are used as fast, low accuracy approximations of the delays within a high complexity integrated circuit. The computational speed of these delay models makes these models approp

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Conclusions, contributing a significant portion of the overall delay. With this increasing importance of on-chip interconnect, more accurate interconnect models are required to correctly design functioning high speed integrated circuits. To date, the IC industry has predominantly modeled the interconnect as one