Titlebook: Offset Reduction Techniques in High-Speed Analog-to-Digital Converters; Analysis, Design and Pedro M. Figueiredo,JoÃo C. Vital Book 2009 Sp

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Integrated Prototypes Using Averaging,polation ADC. Cascaded folding stages and interpolation are used to reduce, respectively, the number of latched comparators and input differential pairs. A S/H samples the input signal, provides amplification by 1.5 and maintains the output voltage stable during half clock cycle.

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Conclusions,ation and occupied area. The two most widely used techniques, . and ., were thoroughly examined and characterized in this book..An overview of the relevant conclusions and novel contributions made throughout this book will now be presented.

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978-90-481-8192-6Springer Science+Business Media B.V. 2009

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Analog Circuits and Signal Processinghttp://image.papertrans.cn/o/image/700716.jpg

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Book 2009l Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed. .