Titlebook: New Algorithms, Architectures and Applications for Reconfigurable Computing; Patrick Lysaght,Wolfgang Rosenstiel Book 2005 Springer-Verlag

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Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture the configure-execute paradigm, the natural paradigm of dynamically reconfigurable computing. This chapter presents a compiler aiming to program the XPP using a subset of the C language. The compiler, apart from mapping the computational structures onto the available resources on the device, splits

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A Low Energy Data Management for Multi-Context Reconfigurable Architecturesnd DSP applications. The main goal of this technique is to diminish application energy consumption. Two levels of on-chip data storage are assumed in the reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to b

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IPsec-Protected Transport of HDTV over IPerforms security protocols such as IPsec; the additional load of complex cryptographic transforms overwhelms modern CPUs when data rates exceed 100 Mbps. This paper describes a network-processing accelerator which overcomes these bottlenecks by offloading packet processing and cryptographic transfor

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