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Titlebook: New Algorithms, Architectures and Applications for Reconfigurable Computing; Patrick Lysaght,Wolfgang Rosenstiel Book 2005 Springer-Verlag

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书目名称New Algorithms, Architectures and Applications for Reconfigurable Computing
编辑Patrick Lysaght,Wolfgang Rosenstiel
视频video
概述Unique record of the state of the art in research into field programmable logic and reconfigurable computing.Exciting research disciplines that span the traditional boundaries of electronic engineerin
图书封面Titlebook: New Algorithms, Architectures and Applications for Reconfigurable Computing;  Patrick Lysaght,Wolfgang Rosenstiel Book 2005 Springer-Verlag
描述.New Algorithms, Architectures and Applications for Reconfigurable Computing. consists of a collection of contributions from the authors of some of the best papers from the Field Programmable Logic conference (FPL’03) and the Design and Test Europe conference (DATE’03). In all, seventy-nine authors, from research teams from all over the world, were invited to present their latest research in the extended format permitted by this special volume. The result is a valuable book that is a unique record of the state of the art in research into field programmable logic and reconfigurable computing...The contributions are organized into twenty-four chapters and are grouped into three main categories: architectures, tools and applications. Within these three broad areas the most strongly represented themes are coarse-grained architectures; dynamically reconfigurable and multi-context architectures; tools for coarse-grained and reconfigurable architectures; networking, securityand encryption applications...Field programmable logic and reconfigurable computing are exciting research disciplines that span the traditional boundaries of electronic engineering and computer science. When the skills
出版日期Book 2005
关键词Embedded System; FPGA; Hardware; Performance; Programmable Logic; RSA; computer; configuration; logic; system
版次1
doihttps://doi.org/10.1007/1-4020-3128-9
isbn_softcover978-1-4419-5264-6
isbn_ebook978-1-4020-3128-1
copyrightSpringer-Verlag US 2005
The information of publication is updating

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Enabling Run-time Task Relocation on Reconfigurable Systemsware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320 × 240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.
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IPsec-Protected Transport of HDTV over IPis highly programmable and can support a variety of offload functions. A sample application is described, wherein production-quality HDTV is transported over IP at nearly 900 Mbps, fully secured using IPsec with AES encryption.
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A Low Energy Data Management for Multi-Context Reconfigurable Architecturesthe reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to be stored in order to reduce energy consumption. We also show that a suitable data scheduling could decrease the energy required to implement the dynamic reconfiguration of the system.
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