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Titlebook: Nanoscaled Semiconductor-on-Insulator Structures and Devices; Steve Hall,Alexei N. Nazarov,Vladimir S. Lysenko Conference proceedings 2007

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发表于 2025-3-21 16:41:35 | 显示全部楼层 |阅读模式
书目名称Nanoscaled Semiconductor-on-Insulator Structures and Devices
编辑Steve Hall,Alexei N. Nazarov,Vladimir S. Lysenko
视频video
概述Reviews by leading experts in SOI nanoscaled electronics.Analysis of prospects of SOI nanoelectronics beyond Moore’s law.Explanation of fundamental limits for CMOS, SOICMOS and single electron technol
丛书名称NATO Science for Peace and Security Series B: Physics and Biophysics
图书封面Titlebook: Nanoscaled Semiconductor-on-Insulator Structures and Devices;  Steve Hall,Alexei N. Nazarov,Vladimir S. Lysenko Conference proceedings 2007
描述This proceedings volume constitutes an archive of the contributions of the key-speakers who attended the NATO Advanced Research Workshop on “Nanoscaled Semiconductor-On-Insulator Structures and devices” held in the Tourist and Recreation Centre “Sudak” (Crimea, Ukraine) from 15 to 19 October 2006. The semiconductor industry has sustained a very rapid growth during the last three decades through impressive technological developments which have resulted in products with higher performance and lower cost per function. After many years of development it is now confidently predicted that semiconductor-on-insulator materials will enter and increasingly be used by manufacturing industry. The wider use of semiconductor (es- cially silicon) on insulator materials will not only enable the benefits of these materials to be demonstrated but, also, will drive down the cost of substrates which, in turn, will stimulate the development of other novel devices and applications. Thus the semiconductor-on-insulator materials of today are not only the basis for modern microelectronics but also for future nanoscale devices and ICs. In itself this trend will encourage the promotion of the skills and idea
出版日期Conference proceedings 2007
关键词Anode; CMOS; FinFET; IC; MOSFET; Nanotube; Potential; Transistor; electronics; heterojunction bipolar transis
版次1
doihttps://doi.org/10.1007/978-1-4020-6380-0
isbn_softcover978-1-4020-6379-4
isbn_ebook978-1-4020-6380-0Series ISSN 1874-6500 Series E-ISSN 1874-6535
issn_series 1874-6500
copyrightSpringer Science+Business Media B.V. 2007
The information of publication is updating

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发表于 2025-3-21 22:03:21 | 显示全部楼层
Status and trends in SOI nanodevicesulti-gate Si, SiGe, Ge and GaAs MOSFETs and Nanowires realized with various channel orientations are also addressed. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined.
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High-κ Dielectric Stacks for Nanoscaled SOI Devicess paper sets out the basic issues and physics associated with both hi- κ/metal gate and UTB from a device perspective, and establishes the advantages associated with merging the two approaches. A review of the state-of the art devices is undertaken also which serves to emphasize the great potential and progress of this technology.
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SiGeC HBTs: impact of C on Device Performance?) on device performance. The devices with low C content (0.45?) exhibit excellent performance and gain up to 500. The results indicate that C content to be used in these devices should be less than 1?.
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Nanowire Quantum Effects in Trigate SOI MOSFETsnsconductance when measured as a function of the gate voltage. These oscillations are visible at low temperature (< 30K) in samples with a 45 × 82nm cross section and at room temperature in devices with a 11nm × 48nm cross section.
发表于 2025-3-23 02:18:40 | 显示全部楼层
Substrate Effect on the Output Conductance Frequency Response of SOI MOSFETsrt the obtained results. It is demonstrated that the appearance of “substrate-related” transitions, their position and amplitude depend strongly on the substrate doping, space-charge conditions at substrate-BOX interface, temperature and moreover become more pronounced with device downscaling.
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