书目名称 | Low-Power High-Level Synthesis for Nanoscale CMOS Circuits | 编辑 | Priyardarsan Patra,Elias Kougianos,Saraju P. Mohan | 视频video | http://file.papertrans.cn/589/588892/588892.mp4 | 概述 | Discusses high-level synthesis fundamentals..Presents a very comprehensive treatment on all aspects of power dissipation..Includes information on power reduction fundamentals, specifically peak power | 图书封面 |  | 描述 | ..Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation..The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the und | 出版日期 | Book 2008 | 关键词 | Architectural power estimation; CMOS; High-level synthesis; Logic gate levels; Low-power synthesis; Nanos | 版次 | 1 | doi | https://doi.org/10.1007/978-0-387-76474-0 | isbn_softcover | 978-1-4419-4554-9 | isbn_ebook | 978-0-387-76474-0 | copyright | Springer-Verlag US 2008 |
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Front Matter |
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,Introduction, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,High-Level Synthesis Fundamentals, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,Power Modeling and Estimation at Transistor and Logic Gate Levels, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,Architectural Power Modeling and Estimation, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,Power Reduction Fundamentals, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,Energy or Average Power Reduction, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,Peak Power Reduction, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,Transient Power Reduction, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,Leakage Power Reduction, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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,Conclusions and Future Direction, |
Saraju P. Mohanty,Nagarajan Ranganathan,Elias Kougianos,Priyadarsan Patra |
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Back Matter |
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