Titlebook: Low Power Networks-on-Chip; Cristina Silvano,Marcello Lajolo,Gianluca Palermo Book 2011 Springer Science+Business Media LLC 2011 Embedded

ALLEY

Interferons

Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study

娴熟

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Adrenaline

CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study

BYRE

Dawdle

JAMB

es not endorse any particular modeling paradigm or software. Rather, the volumes in the series will emphasize simplicity of lea- ing, expressive power, and the speed of execution as priorities 978-1-4757-8052-9978-0-387-21555-6Series ISSN 2199-2606 Series E-ISSN 2199-2614

流眼泪

Ciprian Seiculescu,Srinivasan Murali,Luca Benini,Giovanni De Michelies not endorse any particular modeling paradigm or software. Rather, the volumes in the series will emphasize simplicity of lea- ing, expressive power, and the speed of execution as priorities 978-1-4757-8052-9978-0-387-21555-6Series ISSN 2199-2606 Series E-ISSN 2199-2614

ELUC

Ambulatory

https://doi.org/10.1007/978-1-4419-6911-8Embedded Systems; High Speed Interconnect; Low Power Design; Network on Chip; On-Chip Communication Arch