| 书目名称 | Learning from VLSI Design Experience | | 编辑 | Weng Fook Lee | | 视频video | | | 概述 | Addresses practical design issues and their workarounds.Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influe | | 图书封面 |  | | 描述 | .This book shares with readers practical design knowledge gained from the author’s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.. | | 出版日期 | Book 2019 | | 关键词 | VLSI Physical Design Automation; CMOS VLSI Design; VLSI Verification; VLSI Testing; Design For Test | | 版次 | 1 | | doi | https://doi.org/10.1007/978-3-030-03238-8 | | isbn_ebook | 978-3-030-03238-8 | | copyright | Springer Nature Switzerland AG 2019 |
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发表于 2025-3-21 16:21:33
