| 书目名称 | Layout Minimization of CMOS Cells |
| 编辑 | Robert L. Maziasz,John P. Hayes |
| 视频video | http://file.papertrans.cn/583/582141/582141.mp4 |
| 丛书名称 | The Springer International Series in Engineering and Computer Science |
| 图书封面 |  |
| 描述 | The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer aided-design (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for area-reducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graph-theoretic concepts that completely characterize the fundamental area minimization problems for series-parallel and nonseries-parallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a one-dimensional array of such cells. Althoug |
| 出版日期 | Book 1992 |
| 关键词 | CMOS; Programmable Logic; circuit; complexity; computer; integrated circuit; logic; manufacturing; model; tra |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4615-3624-6 |
| isbn_softcover | 978-1-4613-6611-9 |
| isbn_ebook | 978-1-4615-3624-6Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Springer Science+Business Media New York 1992 |
|Archiver|手机版|小黑屋|
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