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Titlebook: Interconnect Technology and Design for Gigascale Integration; Jeff Davis,James D. Meindl Book 2003 Springer Science+Business Media New Yor

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书目名称Interconnect Technology and Design for Gigascale Integration
编辑Jeff Davis,James D. Meindl
视频video
概述Is the cumulative effort from academic researchers at Georgia Tech, MIT, and Stanford, as well as from industry researchers at IBM T.J. Watson Research Center, LSI Logic, and SUN microsystems.It spans
图书封面Titlebook: Interconnect Technology and Design for Gigascale Integration;  Jeff Davis,James D. Meindl Book 2003 Springer Science+Business Media New Yor
描述.Interconnect Technology and Design for Gigascale Integration. is the cumulative effort from academic researchers at Georgia Tech, MIT, and Stanford, as well as from industry researchers at IBM T.J. Watson Research Center, LSI Logic, and SUN microsystems. The material found in this book is unique in that it spans IC interconnect topics ranging from IBM‘s revolutionary copper process to an in depth exploration into interconnect-aware computer architectures. This broad swath of topics presented by leaders in the research field is intended to provide a comprehensive perspective on interconnect technology and design issues so that the reader will understand the implications of the semiconductor industry‘s next substantial milestone - gigascale integration.
出版日期Book 2003
关键词LSI; Transistor; architecture; complexity; computer-aided design (CAD); integrated circuit; modeling
版次1
doihttps://doi.org/10.1007/978-1-4615-0461-0
isbn_softcover978-1-4613-5088-0
isbn_ebook978-1-4615-0461-0
copyrightSpringer Science+Business Media New York 2003
The information of publication is updating

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https://doi.org/10.1007/978-1-4615-0461-0LSI; Transistor; architecture; complexity; computer-aided design (CAD); integrated circuit; modeling
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Interconnect Opportunities for Gigascale Integration (GSI),gies have guided these advances: 1) scaling down minimum feature size, 2) increasing die size, and 3) enhancing packing efficiency (defined as the number of transistors or length of interconnect per minimum feature square of silicon area). Scaling of transistors reduces their cost, intrinsic switchi
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Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductance,creasing clock frequency combined with growing chip area results in the ratio of global wire delay to gate delay increasing at a super-linear rate. For sub-0.25 .m technology at gigahertz-scale clock frequencies, interconnects may exhibit transmission line behavior. This has spawned the need to accu
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Stochastic Multilevel Interconnect Modeling and Optimization,rative to gain thorough understanding of wiring requirements for present and projected gigascale integrated (GSI) systems. It has been shown that optimized logic networks have certain collective properties that can be described with Rent’s Rule. Using this well-established empirical relationship as
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