Titlebook: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation; 17th International W Nadine Azémard,Lars Sven

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Logic Style Comparison for Ultra Low Power Operation in 65nm TechnologyPL (MTCPL), in ultra low supply voltage conditions is compared to CMOS+, Dual Value Pass transistor Logic, and static CMOS in the same environment. The results show that although CMOS+ demonstrates the best energy delay characteristics for ultra low-power design, MTCPL yields the best energy at low data activities.

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Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurementson including peripherals. Experiments on a complex ARM9 platform show that our model estimates are in error by less than 10% from real system consumption, which is precise enough for source code application design, while simulation speed remains fast.

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The Design and Implementation of a Power Efficient Embedded SRAMneeded by the low swing write technique. The new SRAM is demonstrated to a factor of 4 improvement in power efficiency over a commercial SRAM macro. It also 30% faster than the commercial SRAM macro with only 3% area overhead.

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A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect performance analysis. The traditional circuit degradation analysis leads to on average 59.3% overestimation. The pin reordering technique can mitigate on average 6.4% performance degradation in our benchmark circuits.