Titlebook: Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation; 10th International W Dimitrios Soudris,Peter Pirsch,Eric

Left-Atrium

粗鲁性质

新鲜

Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receiversthe basic components of almost every digital receiver, are used. The experimental results prove that the application of the proposedtec hnique introduces significant power savings, while negligibly increasing area andcritical path.

猛击

Early Power Estimation for System-on-Chip Designseration approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time.

提升

故意钓到白杨

ALIAS

Impact of Voltage Scaling on Glitch Power Consumptioncted on designs, which experience glitching, at supply voltages in the range from 3.5 V to 1.0 V. The results show that the dynamic power consumption caused by glitches will, in comparison to the dynamic power consumption of transitions, be at least as important in the future as it is today.

过于平凡

978-3-540-41068-3Springer-Verlag Berlin Heidelberg 2000

COLIC

genesis

0302-9743 Overview: Includes supplementary material: 978-3-540-41068-3978-3-540-45373-4Series ISSN 0302-9743 Series E-ISSN 1611-3349