Titlebook: Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation; 10th International W Dimitrios Soudris,Peter Pirsch,Eric

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书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation影响因子(影响力)




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation影响因子(影响力)学科排名




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation网络公开度




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation网络公开度学科排名




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation被引频次




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation被引频次学科排名




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation年度引用




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation年度引用学科排名




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation读者反馈




书目名称Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation读者反馈学科排名

航海太平洋

Accurate Power Estimation of Logic Structures Based on Timed Boolean Functionsed parameters, under real delay model, are derived. The chosen gate model allows accurate estimation of the functional and spurious (glitches) transitions, leading to accurate power estimation. Comparative study and analysis of benchmark circuits demonstrates the accuracy of the proposed method.

我不重要

Degradation Delay Model Extension to CMOS Gatesring a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.

放纵

Second Generation Delay Model for Submicron CMOS ProcessO coupling, load and input ramp effects. A first model is deduced for inverters and then extended to logic gates through a reduction protocol of the serial transistor array. Validations are given, on a 0.18μm process, by comparing values of simulated (HSPICE) and calculated delay for different configurations of inverters and gates.

Ringworm

Asynchronous First-in First-out Queuesfirst-output queues, which are fundamental component in most recent proposals for asynchronous processors. Different strategies have been refined and evaluated using the handshake circuits methodology.

FAZE

Defense

Framework for High-Level Power Estimation of Signal Processing Architecturesct-oriented design of the estimation tool. Main features are: an easy macromodule extension, the implementation of a Verilog HDL subset, and a moderate model complexity. Estimation results obtained using the framework for development of a discrete cosine transform compare to the deviation of power consumption imposed by their data dependency.

Mutter

A Holistic Approach to System Level Energy Optimizationtic look at power optimization from an integrated hardware and software perspective. This paper envisions the tools and methodologies that will become necessary for performing such optimizations. It also presents insights into the interaction and influence of hardware and software optimizations on system energy.

Heart-Attack

Expand

Semi-modular Latch Chains for Asynchronous Circuit Designhem into a restricted gate array ASIC library, such as IBM SA-12E that consists of logic gates with maximum four inputs and includes AO12, AOI12, OA12 and OAI12. The method is illustrated by new implementations of practically useful asynchronous circuits: a toggle element and an edge-triggered latch controller.