Titlebook: Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors; José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Bo

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Substance

José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Becker

CLAP

José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Becker

使苦恼

José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Becker

GILD

Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

Obverse

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Introduction,tant topic of interest. In the early ages of computers, their usage was very specific calculations, and aimed at activities such as military applications, precise calculations, and space missions. An error in these applications working in such harsh environments, and sometimes even in remote places

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Fault Tolerance Techniques for Processors,ware-based techniques and (3) hybrid techniques. Fault tolerance techniques can be applied at different levels of implementation, starting from the software level down to the architecture description level, the logical and transistor level, until the layout level. In this book, we will focus on hybr

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BRIDE

Simulation Fault Injection Experimental Results,by adding upsets when simulating a given system in commercial simulators, such as ModelSim from Mentor or iSim from Xilinx, or open source simulators, such as Spice. They are able to provide the best control over the experiment. This characteristic is because the simulation can be stopped at any sim