| 书目名称 | High-Level Verification | | 副标题 | Methods and Tools fo | | 编辑 | Sudipta Kundu,Sorin Lerner,Rajesh K. Gupta | | 视频video | | | 概述 | Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification.Uses a combination of formal techniques to do scalable verification of syste | | 图书封面 |  | | 描述 | Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of sys | | 出版日期 | Book 2011 | | 关键词 | Design Automation; Design Validation; Design Verification; EDA; Embedded Systems; Equivalence Checking; He | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4419-9359-5 | | isbn_softcover | 978-1-4939-0101-2 | | isbn_ebook | 978-1-4419-9359-5 | | copyright | Springer Science+Business Media, LLC 2011 |
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发表于 2025-3-21 17:15:18
