Titlebook: Emerging Technology Trends in Electronics, Communication and Networking; Select Proceedings o Rasika Dhavse,Vinay Kumar,Salvatore Monteleon

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Sardar M. N. Islam,Christine Suet Yee Maksed optimization is explored. Further, the logical effort-based delay reduction, a super buffer-based delay reduction, and delay of an un-optimized circuit are also compared. The effect of technology on logical effort method for each parameter in the deep submicron sizes has also been investigated in this research work.

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Millimeter Wave Overmoded Circular Waveguide Tapers for ECRH Applicationsximately 107λ. However, raised cosine tapers may provide lower insertion loss, but linear tapers with moderate values of diameter ratio may be attractive because of its simplicity in fabrication. Both the tapers are designed and simulated using computer simulation technology (CST) Microwave Studio software.

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Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologiessed optimization is explored. Further, the logical effort-based delay reduction, a super buffer-based delay reduction, and delay of an un-optimized circuit are also compared. The effect of technology on logical effort method for each parameter in the deep submicron sizes has also been investigated in this research work.

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Conference proceedings 2023working, ET2ECN 2021. The volume covers a wide range of topics, including electronic devices, VLSI design and fabrication, photo electronic systems and applications, integrated optics, embedded systems, wireless communication, optical communication, free-space optics, signal processing, image/audio/

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Millimeter Wave Overmoded Circular Waveguide Tapers for ECRH Applicationsrent diameters (ø63.5 and ø31.75 mm) of transmission line components has been carried out. Design parameter of taper is optimized using coupling theory in such a manner that it provides an appropriate match between input and output of transition with lower spurious modes conversion. There are linear

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Comparison of Total Ionizing Dose Effect on Tolerance of SCL 180 nm Bulk and SOI CMOS Using TCAD Simology, power consuming, expensive, and bulky triple modular redundancy and shielding techniques are required to address radiation related issues. In this work, we simulate Semi-Conductor Laboratory (SCL) 180 nm silicon on insulator (SOI) and Bulk NMOS device for comparative study of TID effects in s