Titlebook: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission; Nereo Markulic,Kuba Raczkowski,Piet Wambacq Book

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Christine Strothotte,Thomas Strothotterage 1.1 dBm output power, and total power consumption of 50 mW. The proposed SSPTX enables extreme spectral efficiency, outperforming similar art in the field. The explored architecture reveals new opportunities in digital TX solutions for next generation wireless links.

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Introduction, performance metrics such as phase noise, spurious content, frequency granularity, and power consumption in context of down/up conversion in accurate receive and transmit modes. An LO is typically implemented within a phase-locked loop (PLL), a system that has been intensively researched for a numbe

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A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis, fractional residue compensation. Since the DTC is put at the input of the system, its resolution, linearity, and phase noise performance introduce the bottleneck for the overall spectral purity. A high-efficiency, low-noise 10-bit DTC with 0.5 ps resolution is designed. Analog sensitivities of the

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A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation,his is achieved thanks to the digital background cancellation of nonlinearities in the PLL phase-error comparison path. This −247-dB FOM PLL is further enhanced for two-point, wideband phase modulation, achieving <−40-dB EVM around a 10-GHz carrier during 10-Mb/s GMSK modulation. Analog nonidealitie

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Conclusion and Future Outlook,f severe design challenges (such as bandwidth limitation and linearity) that need to be carefully tackled when targeting high-speed communication. This book offers contributions to the state of the art in fractional frequency synthesis and polar transmitter design. The presented material is built ar

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