Titlebook: Design, Analysis and Test of Logic Circuits Under Uncertainty; Smita Krishnaswamy,Igor L. Markov,John P. Hayes Book 2013 Springer Science+

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Superposition with Structural Inductionncreased vulnerability to soft errors and other sorts of uncertainty in circuit behavior. We also provide an overview of previous work on soft-error rate (SER) analysis, fault-tolerant design, soft-error rate testing, and probabilistic circuit analysis.

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A Neurally-Guided, Parallel Theorem Provere use of PTMs in capturing various sorts of errors inherent in nanocircuits.We also show the use of PTMs in deriving polynomial approximations for circuit error probabilities in terms of gate error probabilities for the purpose of determining thresholds of acceptable gate error for specific circuits.

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Introduction,ncreased vulnerability to soft errors and other sorts of uncertainty in circuit behavior. We also provide an overview of previous work on soft-error rate (SER) analysis, fault-tolerant design, soft-error rate testing, and probabilistic circuit analysis.

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