Titlebook: Defect and Fault Tolerance in VLSI Systems; Volume 2 C. H. Stapper,V. K. Jain,G. Saucier Book 1990 Springer Science+Business Media New York

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Probabilistic Analysis of Memory Repair and Reconfiguration Heuristicsith spare rows and columns. By studying the probability of successful application of these heuristics, we are able to make statements about their average performance. Finally, an algorithm which almost always runs in polynomial time based on an appropriate failure rate is presented.

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Arithmetic-Based Diagnosis in VLSI Array Processorseasy-testable techniques allow an array to be modified in such a way that the testing time is independent of the array size [1] – [4]. This approach exploits the structural properties of iterative arrays which are modeled as combinational circuits. Different testability conditions have been establis

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Yield Improvement Through X-RAY Lithographyes rapidly as their size decreases, not only because of the larger number of small airborne particulates but also because of the particulates from tools and semiconductor materials. Even with better clean rooms, this larger defect density can cause drastic yield reductions unless specific measures a

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Reliability Analysis of Application-Specific Architecturesmportant issue. For example, empirical studies have shown that as a technology undergoes constant-current scaling by a factor of α., the median time to failure due to metal electromigration will be diminished by a factor of α. [1]. In addition, an increase in clock rate requires that nodes be charge

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An Integer Linear Programming Approach to General Fault Covering Problemstion problem for which there are known methods of solution. To demonstrate the effectiveness of the integer linear programming approach, we studied three different fault covering problems, namely, the fault covering problems for redundant RAMs, the fault covering problems for arrays of RAMs with sha

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Systematic Extraction of Critical Areas From IC Layouts...., ..

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on­ tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.978-1-4757-9959-0978-1-4757-9957-6

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https://doi.org/10.1007/978-981-13-0782-9tion problem for which there are known methods of solution. To demonstrate the effectiveness of the integer linear programming approach, we studied three different fault covering problems, namely, the fault covering problems for redundant RAMs, the fault covering problems for arrays of RAMs with sha