Titlebook: Constructive Side-Channel Analysis and Secure Design; 15th International W Romain Wacquez,Naofumi Homma Conference proceedings 2024 The Edi

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On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injectioning faults into target circuits. These days, EMFI draws attention as a real threat to cryptographic circuits because of its inherent advantages. Although EMFI has become popular, there are only a few works on EMFI at the lowest physical level. In this paper, we experimentally show that EMFI induces

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EFFLUX-F2: A High Performance Hardware Security Evaluation Boardlso being applied in fields such as AI and Machine Learning to investigate possible threats. Security evaluations are reliant on standard test setups including commercial and open-source evaluation boards such as, SASEBO/SAKURA and ChipWhisperer. However, with shrinking design footprints and overlap

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Practical Improvements to Statistical Ineffective Fault Attackss, which require both faulty and correct ciphertexts under the same key, SFA leverages only faulty ciphertexts. In CHES 2018, more powerful attacks called Statistical Ineffective Fault Attacks (SIFA) have been proposed. In contrast to the previous fault attacks that utilize faulty ciphertexts, SIFA

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CAPABARA: A Combined Attack on CAPA to protecting against passive physical attacks (. side-channel analysis (SCA)), the landscape of protection against other types of physical attacks remains a challenge. Fault attacks (FA), though attracting growing attention in research, still lack the prevalence of provably secure designs when com

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Exploring Multi-task Learning in the Context of Masked AES Implementationss pointed out a significant challenge: overcoming the initial learning plateau. This paper discusses the advantages of multi-task learning to break through the initial plateau consistently. We investigate different ways of applying multi-task learning against masked AES implementations (via the ASCA

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The Need for MORE: Unsupervised Side-Channel Analysis with Single Network Training and Multi-output sion (MOR) approach for non-profiling side-channel analysis. Then, we significantly improve its performance by updating the loss function and distinguisher, then employing a novel concept of validation set to reduce overfitting. We denote our approach as MORE - Multi-Output Regression Enhanced, whic

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Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generatorsvices exploits the noise jitter accumulation with ring oscillators. The Set-Reset latch (SR-latch) TRNG is another type which exploits the state of latches around metastability. In this TRNG the dynamic noise is extracted by analysing the convergence state of the related latch. The advantage is its

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