Titlebook: Computer-Aided Design and VLSI Device Development; Kit Man Cham,Soo-Young Oh,John L. Moll Book 1986 Springer Science+Business Media New Yo

偏见

Banister

Gunnar Eliasson,Pontus Braunerhjelm down of geometrical dimensions introduces two-dimensional and even three-dimensional effects both in transistor behavior and in the parasitics. The scaling of interconnections is usually emphasized primarily in the width and spacing of the lines. For example, the line/space design rule (in micromet

FOIL

Methodology in Computer-Aided Design for Process and Device Development Hewlett-Packard Laboratories. In this chapter, CAD is discussed from the user point of view. The methodology for using the simulation tools in the most effective way is presented. Then case studies will be presented in the following chapters which show in detail how simulation tools are used in device designs.

巧办法

Transistor Design for Submicron CMOS Technologynology will first be discussed. Then the concerns for the design of n and p-channel MOSFETs with submicron channel lengths will be discussed. Using simulations, the values of the critical device parameters are determined which will minimize leakage problems in submicron transistors.

fleeting

Process Simulationechnologies. When coupled with a device analysis program, a process simulator has proven to be a powerful design tool because the process sensitivity to device parameters can be easily extracted by simple changes made to processing conditions in computer inputs. [2.1].

CHOKE

Device Simulation the device reliability, e.g., reducing the electric field at the drain of the MOSFET. Therefore, in the development of VLSI MOS technology, it is essential to be able to simulate the electrical characteristics of devices which have complicated structures. The GEMINI program provides this capability.

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摇曳

Development of Isolation Structures for Applications in VLSI 2 µm or less, narrow width effects become a major issue. [10.2]–[10.5]. These effects are dependent on the isolation structures since the channel width of the device is defined by the field isolation. Many novel isolation structures have been investigated for applications in VLSI [10.6]–[10.14].

CARE

Harold Paredes-Frigolett,Andreas Pykaortance of secondary physical effects can be seen. Device width will not be scaled, the current drive capability will be expressed for a fixed width. Breakdown and punchthrough voltages must be sufficiently greater than the supply voltage so that reliability is not a problem. For this example, power density is not a limitation.

Creditee

MOSFET Scaling by CADDETortance of secondary physical effects can be seen. Device width will not be scaled, the current drive capability will be expressed for a fixed width. Breakdown and punchthrough voltages must be sufficiently greater than the supply voltage so that reliability is not a problem. For this example, power density is not a limitation.