Titlebook: Computer Architecture; Workshop of the Gese W. Händler,Robert K. Bell Conference proceedings 1976 Springer-Verlag Berlin · Heidelberg 1976

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https://doi.org/10.1007/978-3-642-81174-6zing program which considers several levels of parallelism transforms a given program into a “maximally parallel asynchronous” program. The resulting program is executed by a hierarchical processor system where each level of parallelism corresponds to a level of processing elements.

Anthrp

Tactics and Strategy in Cancer Treatment The first part describes the problems arising in a pipeline computer executing programs with conditional branch instructions, and gives proposals how to solve them. In the second part the connection of a cache-memory with a pipeline is discussed. Such a connection increases the number of instructions which are suited for advance execution.

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Structured Design for Structured Computer Architecture,erarchisation of the activities implemented implies that those of high level control those of lower level. Also, the consequence of technological maturity is that, at each design level, components are available, and an implementation is achieved by the assembling of components, possibly of different technology.

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A Concept for Hardwired Main Storage Management,dently of the CPU. Information about the occupied/released status of the storage cells is held in two separate bit planes in the form of tag bits. The processor handles requests for and releases of storage space, returning and receiving base addresses, respectively.

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附录

A Processor System for Multiprocessing,ntrol and execution is proposed. The function of the essential units is described and some simulation results are considered. The performance of the processor system, dependent on the number of instruction streams and execution units is investigated.

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