Titlebook: Asynchronous Circuit Design for VLSI Signal Processing; Teresa H. Meng,Sharad Malik Book 1994 Kluwer Academic Publishers 1994 Analysis.VLS

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Performance of Iterative Computation in Self-Timed Rings,it. Instead, self-timed structures can compute without clock or latch delays. In particular, a self-timed ring is a loop of logical stages that, after initialization with operands, computes multiple cycles of an iterative computation without further external handshaking. Viewed as a whole, a self-ti

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Bravado

Designing Self-Timed Systems Using Concurrent Programs,ditional clocked circuits in a variety of applications. However, design of self-timed systems has long been considered too difficult because of the specialized circuits required and the lack of tools available to help the designer explore the potential of such systems. This article describes one app

Stress

Synthesis of Hazard-Free Control Circuits from Asynchronous Finite State Machines Specifications,is of hazard-free control circuits under the unbounded delay model. AFSM are useful for the specification of sequential behavior involving choices. In contrast, models such Signal Transition Graphs (STGs) are more amenable to the specification of deterministic concurrent behavior. AFSM specification

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Specification, Synthesis, and Verification of Hazard-Free Asynchronous Circuits,u [.] is too restrictive for specifying general asynchronous behavior and propose extensions to the STG which allow for more general and compact representation. Second, we show that syntactic constraints on STGs are not sufficient to guarantee hazard-free implementations under the unbounded gate del

inclusive

A Generalized State Assignment Theory for Transformations on Signal Transition Graphs,rantee . conditions for a state graph assignment to result in a transformed state graph that is free of critical races. Performing transformations at the state graph level has the advantage that the requirements imposed on the initial STG are very weak. Unlike previous methods, the initial STG need

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Hiatus

Linear Programming for Hazard Elimination in Asynchronous Circuits, Program. This article describes how to analyze the STG specification and the synthesized circuit, using bounded delay information, to formulate the problem and use a branch-and- bound procedure to solve it. Known information about the environment delays can be expressed as time bounds on the extern

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