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Titlebook: Asynchronous Circuit Design for VLSI Signal Processing; Teresa H. Meng,Sharad Malik Book 1994 Kluwer Academic Publishers 1994 Analysis.VLS

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期刊全称Asynchronous Circuit Design for VLSI Signal Processing
影响因子2023Teresa H. Meng,Sharad Malik
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图书封面Titlebook: Asynchronous Circuit Design for VLSI Signal Processing;  Teresa H. Meng,Sharad Malik Book 1994 Kluwer Academic Publishers 1994 Analysis.VLS
影响因子.Asynchronous Circuit Design for VLSI Signal Processing.is a collection of research papers on recent advances in the area ofspecification, design and analysis of asynchronous circuits andsystems.This interest in designing digital computing systems withouta global clock is prompted by the ever growing difficulty in adoptingglobal synchronization as the only efficient means to system timing..Asynchronous circuits and systems have long held interest for circuitdesigners and researchers alike because of the inherent challengeinvolved in designing these circuits, as well as developing designtechniques for them. The frontier research in this area can be tracedback to Huffman‘s publications `The Synthesis of Sequential SwitchingCircuits‘ in 1954 followed by Unger‘s book, `Asynchronous SequentialSwitching Circuits‘ in 1969 where a theoretical foundation forhandling logic hazards was established. In the last few years agrowing number of researchers have joined force in unveiling themystery of designing correct asynchronous circuits, and better yet,have produced several alternatives in automatic synthesis andverification of such circuits. .This collection of research papers represents a bala
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A Generalized State Assignment Theory for Transformations on Signal Transition Graphs,ree choice net and a 1-safe net into a correct 2-safe net are feasible. Addition of transitions that do not follow the Petri net firing rule is also possible. Even though our method can search a large solution space, we will show that it is possible to solve the problem in an exact way in acceptable
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Asynchronous Circuit Design for VLSI Signal Processing978-1-4615-2794-7
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tablished. In the last few years agrowing number of researchers have joined force in unveiling themystery of designing correct asynchronous circuits, and better yet,have produced several alternatives in automatic synthesis andverification of such circuits. .This collection of research papers represents a bala978-1-4613-6208-1978-1-4615-2794-7
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Editorial,nchronous circuits and systems. This interest in designing signal processing systems without a global clock is prompted by the ever growing difficulty in adopting global synchronization as the only efficient means to system timing.
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Self-Timed Logic Using Current-Sensing Completion Detection (CSCD),pletion Detection, CSCD, allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number o
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