Titlebook: Architecture of Computing Systems; 34th International C Christian Hochberger,Lars Bauer,Thilo Pionteck Conference proceedings 2021 Springer

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V. Suma,Noureddine Bouhmala,Haoxiang Wangow runtime libraries such as DARTS and OCR. Even though our environment is not yet optimized, we found that DRT outperforms the above runtime frameworks in terms of execution time. We also give an evaluation of the time and complexity to develop DF-Threads examples in DRT compared to the approach of

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How Can Evolutionary Economics Evolve?ts the power-gating to CPU execution phases. Detailed simulations of the governor are carried out over a range of benchmarks, the CPG governor shows on average an 11% reduction in energy consumption and an 8% increase in energy efficiency over a state-of-the-art DVFS governor. Using these techniques

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Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Syforms. While our results show promising feasibility evidence, they also reveal shortcomings which should be addressed before these toolsets become fit for developing critical systems. We propose certain improvements that have to be incorporated in these tools to achieve this goal. By implementing ou

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DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Modelow runtime libraries such as DARTS and OCR. Even though our environment is not yet optimized, we found that DRT outperforms the above runtime frameworks in terms of execution time. We also give an evaluation of the time and complexity to develop DF-Threads examples in DRT compared to the approach of

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Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone Systemossible in self-healing scenarios..Although this priority-based AHS extension’s time bounds have previously been studied, its behavior has not yet been thoroughly evaluated. In this paper, we thus present evaluations of this extension, confirming and refining the known time bounds.

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Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-Gatingts the power-gating to CPU execution phases. Detailed simulations of the governor are carried out over a range of benchmarks, the CPG governor shows on average an 11% reduction in energy consumption and an 8% increase in energy efficiency over a state-of-the-art DVFS governor. Using these techniques

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Locality: The 3rd Wall and the Need for Innovation in Parallel Architecturesidence of a third wall dealing with data locality, which is prevalent in data intensive applications where computation is dominated by memory access and movement – not flops, Such apps exhibit large sets of often persistent data, with little reuse during computation, no predictable regularity, signi

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Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasksry level and generates worst-case timing and memory access profiles. These profiles can then be combined to perform an interference analysis at the task system level, as part of a multi-core Worst-Case Response Time (WCRT) analysis. In this paper we introduce a formal description of the models and a